1. Technical Field
The disclosed embodiments relate to high frequency dividers involving differential latches.
2. Background Information
High frequency dividers see use in many applications including uses in radio communications circuitry. In one example, a high frequency divider involving differential latches receives an input signal and frequency divides the input signal, thereby generating two lower frequency output signals: an in-phase (I) output signal, and a quadrature (Q) output signal. The frequencies of the I and Q output signals may, for example, be half the frequency of the input signal. The divider divides by the integer two. The Q output signal is of the same frequency as the I output signal, but has a ninety degree phase shift with respect to the I output signal. Such a divider may, for example, be used to supply I and Q signals to a mixer in a radio receiver. By changing the frequency of the I and Q signals as supplied to the mixer, the receiver can be tuned to downconvert signals of different frequencies. This is but one application of a high frequency divider of this type. A high frequency divider may also see use in the loop divider of a Phase-Locked Loop (PLL) within a local oscillator, or in frequency dividing a signal in other places in the radio circuitry.
FIG. 1 (Prior Art) is a diagram of one type of conventional divider. This divider 1 includes two differential latches 2 and 3. Divider 1 receives a differential input signal VO involving signal VOP on conductor 4 and signal VON on conductor 5. The “VO” letters in these signal names indicates that the signal is a VCO output signal. Divider 1 receives the differential input signal VO and generates therefrom two differential output signals I and Q. Differential output signal I involves signal IP on conductor 6 and signal IN on conductor 7. Differential output signal Q involves signal QP on conductor 8 and signal QN on conductor 9. Although the circuit of FIG. 1 operates satisfactorily in some applications, it has limitations including an undesirably low frequency operating range. For additional information on a divider of the type of divider 1, see U.S. Pat. No. 7,521,976.
FIG. 2 (Prior Art) is a diagram of another type of conventional divider. Divider 10 includes two differential latches 11 and 12. Divider 10 receives a differential input signal VO involving signal VOP on conductor 13 and signal VON on conductor 14. Divider 10 generates two differential output signals I and Q. Differential output signal I involves signal IP on conductor 15 and signal IN on conductor 16. Differential output signal Q involves signal QP on conductor 17 and signal QN on conductor 18. Dividers of the circuit topology of divider 10 can be implemented and controlled to have a relatively wide frequency operating range, but at higher frequencies the voltage swing of the output signals may decrease in an undesirable manner and the circuit may consume an increased amount of current. In applications such as in a receiver of a battery-powered cellular telephone, it may be desired to operate a divider that generates low phase noise I and Q signals of a high frequency such as a few gigahertz or more, without consuming large amounts of power and without suffering drawbacks associated with low voltage swings of the output signals.